A dynamic random access memory (DRAM) is a volatile memory device that stores data at respective cells each of which comprises one transistor and one capacitor. An input/output operation of data, which is a basic function of a DRAM cell, is performed by selecting a predetermined word line and a column selection signal, wherein the word line is connected to a gate of the transistor in the memory cell.
Recently, as the DRAM becomes a mass storage device with high-speed performance, the DRAM typically employs a sub word line driver for driving a word line faster and a hierarchical input/output structure of a data line, i.e., a local input/output scheme and a global input/output scheme.
A data input/output line for reading and writing the data of the DRAM cell having the hierarchical input/output structure includes a segment input/output line (SIO), a local input/output line (LIO), a global input/output line (GIO), and so forth.
Considering the role of each data input/output line according to the read path, the segment input/output line (SIO) is a data input/output line where the data unit of a cell bit line selected by the word line and the column selection signal is loaded after it is amplified.
Thereafter, the data unit loaded on the segment input/output line (SIO) is loaded on the local input/output line (LIO) and, thereafter, it is applied to an input/output sense amplifier (IOSA). Herein, the local input/output line (ILO) shares the segment input/output lines (SIO) of cell segment blocks which are divided for every bit line sense amplifier (BLSA) of a bank.
The data unit amplified by the input/output sense amplifier (IOSA) is loaded on the global input/output line (GIO). The data unit loaded on the global input/output line (GIO) is output through a desired data pad (DQ0, DQ1, DQ2, DQn-1) by means of an output driver so that a read operation is completed. An operation for writing external data input on the memory cell is performed such that the external data input through the data pad (DQ0, DQ1, DQ2, . . . , DQn-1) is stored in the memory cell after it is transmitted to a write driver.
FIG. 1 is a block diagram of a conventional structure of a global data input/output line.
Referring to FIG. 1, data transmitted from a bank 10 is loaded on a global input/output line (GIO) 1 via a data bus sense amplifier (DBSA) 20. The data loaded on the global input/output line (GIO) 30 is transmitted to a register 30, and thereafter, it is output to an exterior through a data pad 40.
As the global input/output line (GIO) 1 is too long, repeater 50, which is configured with two inverters, is inserted in the global input/output line.
However, in the conventional structure of FIG. 1, since 16 global input/output lines (GIO<0:15>) are connected to the data pad (DQ<0:15>) for transmitting 16-bit data, the length of each global input/output lines (GIO<0:15>) is different from one another. As a result, data skew among the data lines occurs when transmitting the data through the respective data lines.
A double data rate (DDR) 2 synchronous DRAM (SDRAM), comprising a plurality of bank structures, simultaneously transmits 64-bit data. The problem of data skew becomes more serious. That is, since 64 global input/output lines (GIO<0:63>) are connected to the data pad (DQ<0:63>), the length differences among respective global input/output data lines (GIO<0:63>) become greater than the conventional case of using 16 data lines. The time difference of data transmission between the fastest data unit and the slowest data unit may be in the order of nano-seconds because the lengths of the data lines for connecting the plurality of banks to the data pad (DQ<0:63>) are also different from one another. As a result, it is difficult for the register 30 to determine when the data transmitted through the global input/output line (GIO) is recognized. Data recognition becomes more and more unstable as the device operates faster and faster.
This problem existing in the memory device may also occur in other devices. For example, it may also occur in a semiconductor device in which a plurality of data are transmitted through a plurality of data lines.